The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. However, problems arise when the high-k metal gate, gate last process causes chemical mechanical polishing (CMP) dishing in open areas, such as areas reserved for forming inductive or other components over a silicon substrate. To reduce the dishing effect, dummy polysilicon gates may be formed in the open areas reserved for forming inductive or other components. This also causes problems because the high-k metal gate, gate last process removes the polysilicon and replaces it with a metal in the dummy gates. Having the low resistance metal in the areas reserved for inductors or other components causes an undesired coupling effect, due to induced eddy currents, between the inductive device and the substrate.
Accordingly, reduced substrate coupling for inductors in semiconductor devices is desired.